Graduated from the University of Auckland with a Bachelors of Engineering with First Class Honours. They are now doing a PhD under Dr. Oliver Sinnen. Their research focuses on the usage of High Level Synthesis for accelerating SKA algorithms through collaboration with the TDT and the University of Manchester.
Field Programmable Gate Arrays (FPGAs) are becoming increasingly prominent in situations which require high performance at a low energy cost. This is due to the low frequency of operation combined with the capability for extremely high parallelism. However, development for FPGAs is often very slow and requires expert hardware knowledge in order to achieve such performance. A growing solution to this problem is the use of high level code for hardware generation, however current techniques often still rely on expert hardware knowledge for fully optimised solutions. One approach to get around this requirement is the separation of functional description and optimisation process. With the SKA as a driving motivation, this work seeks to investigate and develop compiler level techniques for simplifying the transition from a functional software description to an optimised co-design; utilising FPGAs for accelerating traditional processors.