People

Peter Baillie

Project Manager, High Performance Computing Research Laboratory at AUT. Peter’s Project Management role spans across both CSP and SDP Consortia as well as being the Project Manager point of contact to SKA Office. Peter is Project Manager for Low Telescope and reports to Project Manager for CSP Consortium, based in Canada. He also liaises with SDP Resource Management Team for all NZA assigned tasks, outputs and reporting. Peter’s assigned FTE allocation, along with NZA FPGA Developers make-up a significant contribution to the CSIRO / ASTRON / AUT collaboration who is responsible for delivering the Low Correlator and Beamformer design and supporting Read more …

Norbert Abel

Senior Research Engineer, High Performance Computing Research Laboratory, AUT. Norbert is an FPGA engineer, working full time on the SKA project, collaborating closely with ASTRON (Netherlands) and CSIRO (Australia) to develop the Low-frequency Correlator and Beamformer (Low.CBF). He completed his PhD at the University of Heidelberg, Germany, working as FPGA engineer for the new particle accelerator FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. His thesis “Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration” focussed on enabling the widespread use of Partial Reconfiguration by controlling it via a high-level language. After finishing his PhD, Norbert Read more …

Vignesh Raja Balu

Junior Research Engineer, Center for Research in Analog and VLSI micro-system Design, Massey University. Vignesh is working full time as an FPGA Verification Engineer in the SKA project. He earned his Masters degree in the field of VLSI Design from SASTRA University, India. He served as an Assistant Professor for eight years, contributing more of his time for research and development in the fields of signal processing and ASIC/FPGA designs.

Piers Harding

Solution Architect, Catalyst. Piers is a contributor to the architectural design, and prototyping of the SDP Middleware responsible for providing the platform and environment that contain the image data processing pipelines. Specific areas of focus are: Containerisation, orchestration, scheduling and resource management in HPC, with Docker,  DCOS, and Kubernetes Large scale monitoring and logging Large scale data queue solutions The efficiency of Shared Services Object Storage in HPC Piers is a long time advocate of Open Source software, and Open Data platforms with contributions to the Perl, Python, Ruby, PHP, R, and SAP communities.

William Kamp

Senior Research Engineer, High Performance Computing Research Laboratory, AUT. William is an FPGA engineer in the HPCRL, working full time on the SKA project, collaborating closely with NRC (Canada) to develop the Mid-frequency Correlator and Beamformer (Mid.CBF), and with CSIRO (Australia) and ASTRON (Netherlands)to develop the Low.CBF, two of the sub elements of the Central Signal Processor (CSP). For the SKA project, he has developed: An efficient serial data interconnect that will operate across the >20,000 internal 26Gbps optical fibre links of the Mid.CBF. A network communication protocol called AXIoE (Advanced eXtensible Interconnect over Ethernet) designed  to extend the internal Read more …

TN Chan

Managing Director of Compucon New Zealand (Modern Technology NZ Limited) TN focuses on the Compute Node architecture and performance investigations. His current effort (May 2018) is reviewing the previous estimations of SDP hardware size based on the SDP Parametric Model and ARL requirements. He was born in Hong Kong, earned a honors degree in Mechanical Engineering from the University of Hong Kong and became a Chartered Engineer in Electrical Engineering for his experience of practicing in electricity power generation.  He was employed by the New Zealand Electricity Department and moved to Wellington in 1985 where he continued to practice in Read more …

David Wilson

David Wilson

Associate Professor, AUT.  Director Inverse Problem Ltd. David Wilson is an Associate Professor in Electrical Engineering at Auckland University of Technology. Prior to joining AUT he was on the faculty at Karlstad University in Sweden following a position at the Swiss Federal Institute of Technology (ETH) in Zürich, Switzerland. His main research interests are modelling, simulation and control of industrial processes. Currently he is a director of the research-based Industrial Information and Control Centre (I2C2) where he manages multi-faceted research projects for international clients such as PETRONAS in Malaysia, and large New Zealand companies such as Transpower and Fonterra. He Read more …

S. M. Rezaul Hasan

Senior Lecturer in Computer Engineering, SEAT – Electronics, Info and Communication Systems in Massey University. Presently he is  the  Director of the Center for Research  in Analog and VLSI microsystems dEsign (CRAVE)  at MasseyUniversity. He received his Ph.D. in Electronics Engineering from the University of California  Los Angeles (UCLA). He was a VLSI design engineer at Xerox Microelectronics Center in El Segundo, California,  where he worked in the design of CMOS VLSI microprocessors for 3 years.  He then moved to the Asia-Pacific region and served several institutions including Nanyang Technological University, Singapore, Curtin University of Technology, Western Australia and Universiti Sains Malaysia, Malaysia. At University Sains Malaysia he held the position of Associate Professor and was the coordinator of the Analog and VLSI research laboratory.  He  spent the Read more …

Andrew Ensor

Director NZ SKA Alliance, High Performance Computing Research Laboratory, AUT. Andrew is the Director of the New Zealand SKA Alliance, coordinating New Zealand’s significant involvement in the design of the SKA. He has been active in the SKA’s Central Signal Processor and in the Science Data Processor design since 2013. He is also the Director of the High Performance Computing Research Laboratory at AUT. For the SKA project, Andrew has: Developed efficient streaming data compression algorithms which helped form the start up company Nyriad. Lead the Survey correlator design team. Worked on optimising FFT algorithms across a range of hardware Read more …

Oliver Sinnen

Senior Lecturer Parallel and Reconfigurable Computing lab, University of Auckland Oliver is a Senior Lecturer in the Department of Electrical and Computer Engineering of the University of Auckland. There, he founded and leads the Parallel and Reconfigurable Computing lab (PARC), which works on various aspects of parallel and high performance computing, including scheduling and resource allocation, software engineering for parallel programming and the use of FPGAs (Field Programmable Gate Arrays) as computing accelerators. Oliver and his team at PARC have been working on the SKA project since 2013. We are contributing to the Central Signal Processor (CSP) element of the SKA Read more …

Willem van Straten

Associate Professor, Institute for Radio Astronomy and Space Research, AUT. Willem is an astronomer with interests in pulsars and Fast Radio Bursts. He is currently a co-Chair of the SKA Science Working Group on Fundamental Physics with Pulsars, and as part of pre-construction he is leading the design of the pulsar timing engine (PST) of the SKA Central Signal Processor (CSP). He is a member of the International Pulsar Timing Array Steering Committee and the Australia-New Zealand SKA Coordination Committee (ANZSCC) Science Advisory Committee; he also co-authored two chapters in the SKA Science Book.  Dr van Straten is a Principal Read more …

Krystine Sherwin

Doctoral Candidate Parallel and Reconfigurable Computing lab, University of Auckland Graduated from the University of Auckland with a Bachelors of Engineering with First Class Honours. They are now doing a PhD under Dr. Oliver Sinnen. Their research focuses on the usage of High Level Synthesis for accelerating SKA algorithms through collaboration with the TDT and the University of Manchester. Research Abstract Field Programmable Gate Arrays (FPGAs) are becoming increasingly prominent in situations which require high performance at a low energy cost. This is due to the low frequency of operation combined with the capability for extremely high parallelism. However, development for FPGAs is Read more …