CSP Archives » Square Kilometre Array Telescope Project

Krystine Sherwin

Doctoral Candidate Parallel and Reconfigurable Computing lab, University of Auckland Graduated from the University of Auckland with a Bachelors of Engineering with First Class Honours. They are now doing a PhD under Dr. Oliver Sinnen. Their research focuses on the usage of High Level Synthesis for accelerating SKA algorithms through collaboration with the TDT and the University of Manchester. Research Abstract Field Programmable Gate Arrays (FPGAs) are becoming increasingly prominent in situations which require high performance at a low energy cost. This is due to the low frequency of operation combined with the capability for extremely high parallelism. However, development for FPGAs is Read more …

Oliver Sinnen

Associate Professor Parallel and Reconfigurable Computing lab, University of Auckland Oliver is an Associate Professor in the Department of Electrical and Computer Engineering of the University of Auckland. There, he founded and leads the Parallel and Reconfigurable Computing lab (PARC), which works on various aspects of parallel and high performance computing, including scheduling and resource allocation, software engineering for parallel programming and the use of FPGAs (Field Programmable Gate Arrays) as computing accelerators. Oliver and his team at PARC have been working on the SKA project since 2013. We are contributing to the Central Signal Processor (CSP) element of the SKA Read more …

Restructuring a RAM Multiplexer for Performance in an Intel Stratix10 FPGA

William H. M. Kamp, Ph.D, High Performance Computing Research Lab, Auckland University of Technology, New Zealand. Context The SKA Mid-frequency Correlator dumps 20100 visibility products from its Matrix style cross correlator function every 190 microseconds. It does this over 20 buses each approximately 312 bits wide, with a total instantaneous bandwidth of over 500 GB/s. This dump of data must be serialised and processed by the long term accumulator to an external DDR4 interface that limits the bandwidth. This is achieved with a debursting buffer that has 20 independent write-ports and a single independent read port. The design requires that the Read more …

Peter Baillie

Project Manager, High Performance Computing Research Laboratory at AUT. Peter’s Project Management role spans across both CSP and SDP Consortia as well as being the Project Manager point of contact to SKA Office. Peter is Project Manager for Low Telescope and reports to Project Manager for CSP Consortium, based in Canada. He also liaises with SDP Resource Management Team for all NZA assigned tasks, outputs and reporting. Peter’s assigned FTE allocation, along with NZA FPGA Developers make-up a significant contribution to the CSIRO / ASTRON / AUT collaboration who is responsible for delivering the Low Correlator and Beamformer design and supporting Read more …

Andrew Ensor

Director NZ SKA Alliance, High Performance Computing Research Laboratory, AUT. Andrew is the Director of the New Zealand SKA Alliance, coordinating New Zealand’s significant involvement in the design of the SKA. He has been active in the SKA’s Central Signal Processor and in the Science Data Processor design since 2013. He is also the Director of the High Performance Computing Research Laboratory at AUT. For the SKA project, Andrew has: Developed efficient streaming data compression algorithms which helped form the start up company Nyriad. Lead the Survey correlator design team. Worked on optimising FFT algorithms across a range of hardware Read more …

Willem van Straten

Associate Professor, Institute for Radio Astronomy and Space Research, AUT. Willem is an astronomer with interests in pulsars and Fast Radio Bursts. He is currently a co-Chair of the SKA Science Working Group on Fundamental Physics with Pulsars, and as part of pre-construction he is leading the design of the pulsar timing engine (PST) of the SKA Central Signal Processor (CSP). He is a member of the International Pulsar Timing Array Steering Committee and the Australia-New Zealand SKA Coordination Committee (ANZSCC) Science Advisory Committee; he also co-authored two chapters in the SKA Science Book. Dr van Straten is a Principal Read more …

William Kamp

Senior Research Engineer, High Performance Computing Research Laboratory, AUT. William is an FPGA engineer in the HPCRL, working full time on the SKA project, collaborating closely with NRC (Canada) to develop the Mid-frequency Correlator and Beamformer (Mid.CBF), and with CSIRO (Australia) and ASTRON (Netherlands)to develop the Low.CBF, two of the sub elements of the Central Signal Processor (CSP). For the SKA project, he has developed: An efficient serial data interconnect that will operate across the >20,000 internal 26Gbps optical fibre links of the Mid.CBF. A network communication protocol called AXIoE (Advanced eXtensible Interconnect over Ethernet) designed to extend the internal Read more …

Computing for SKA Colloquium (C4SKA) 2018: Towards Construction

Thursday 15 – Friday 16 February 2018. Venue: Sir Paul Reeves Building WG404, AUT City Campus. The Local Organising Committee warmly invites you to attend the annual Colloquium hosted by the New Zealand SKA Alliance in conjunction with AUT’s School for Engineering, Computer and Mathematical Sciences. It brings together industry and academics working on the design of computer systems for the SKA – the mega science project of the 21st century to build the world’s largest and most sensitive radio telescope. This is an opportunity to hear from the experts involved in the design phase and learn about the range of solutions Read more …