Krystine Sherwin

Doctoral Candidate Parallel and Reconfigurable Computing lab, University of Auckland Graduated from the University of Auckland with a Bachelors of Engineering with First Class Honours. They are now doing a PhD under Dr. Oliver Sinnen. Their research focuses on the usage of High Level Synthesis for accelerating SKA algorithms through collaboration with the TDT and the University of Manchester. Research Abstract Field Programmable Gate Arrays (FPGAs) are becoming increasingly prominent in situations which require high performance at a low energy cost. This is due to the low frequency of operation combined with the capability for extremely high parallelism. However, development for FPGAs is Read more …

Oliver Sinnen

Associate Professor Parallel and Reconfigurable Computing lab, University of Auckland Oliver is an Associate Professor in the Department of Electrical and Computer Engineering of the University of Auckland. There, he founded and leads the Parallel and Reconfigurable Computing lab (PARC), which works on various aspects of parallel and high performance computing, including scheduling and resource allocation, software engineering for parallel programming and the use of FPGAs (Field Programmable Gate Arrays) as computing accelerators. Oliver and his team at PARC have been working on the SKA project since 2013. We are contributing to the Central Signal Processor (CSP) element of the SKA Read more …

MiniZed SpeedWay Design Workshops August 2018

Postponed to August 2018. NZA is hosting the MiniZed SpeedWay Design Workshops™ run by Avnet with 4 one-day courses. The MiniZed SpeedWay Design Workshops™ help engineers jump start the development of Xilinx All Programmable SoC products. The courses revolves around the single-core Xilinx® Zynq®-7000 All Programmable SoC device, though the training can be utilised across all Xilinx SoCs. The targeted board is the Avnet MiniZed™ Zynq SoC development board, a cost optimized prototyping platform perfect for embedded vision and Industrial IoT systems. These one-day instructional programs will train engineers on the latest design flows using Xilinx’s Vivado® Design Suite through a Read more …

Restructuring a RAM Multiplexer for Performance in an Intel Stratix10 FPGA

William H. M. Kamp, Ph.D, High Performance Computing Research Lab, Auckland University of Technology, New Zealand. Context The SKA Mid-frequency Correlator dumps 20100 visibility products from its Matrix style cross correlator function every 190 microseconds. It does this over 20 buses each approximately 312 bits wide, with a total instantaneous bandwidth of over 500 GB/s. This dump of data must be serialised and processed by the long term accumulator to an external DDR4 interface that limits the bandwidth. This is achieved with a debursting buffer that has 20 independent write-ports and a single independent read port. The design requires that the Read more …

Vignesh Raja Balu

Junior Research Engineer, Center for Research in Analog and VLSI micro-system Design, Massey University. Vignesh is working full time as an FPGA Verification Engineer in the SKA project. He earned his Masters degree in the field of VLSI Design from SASTRA University, India. He served as an Assistant Professor for eight years, contributing more of his time for research and development in the fields of signal processing and ASIC/FPGA designs.

Norbert Abel

Senior Research Engineer, High Performance Computing Research Laboratory, AUT. Norbert is an FPGA engineer, working full time on the SKA project, collaborating closely with ASTRON (Netherlands) and CSIRO (Australia) to develop the Low-frequency Correlator and Beamformer (Low.CBF). He completed his PhD at the University of Heidelberg, Germany, working as FPGA engineer for the new particle accelerator FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. His thesis “Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration” focussed on enabling the widespread use of Partial Reconfiguration by controlling it via a high-level language. After finishing his PhD, Norbert Read more …