HPCRL Archives » Square Kilometre Array Telescope Project

Mid-Year-Mini C4SKA Colloquium – 12 July 2018

The New Zealand SKA team welcomed 50 participants to share in the excitement of the New Zealand team at their Mid-Year-Mini Public Seminar on Thursday 12 July 2018, from 1:00pm to 5:30pm. AUT University, Building WG, Room 404, Mayoral Drive, between Wakefield Street and Wellesley Street East, Auckland. The seminar contained updates on science and computing related to the international SKA project to which New Zealand is in its 4th year of contribution. The New Zealand Alliance team members were there for face to face discussions of topics of interest. The seminar included presentations on both the Science of the Universe and Read more …

Restructuring a RAM Multiplexer for Performance in an Intel Stratix10 FPGA

William H. M. Kamp, Ph.D, High Performance Computing Research Lab, Auckland University of Technology, New Zealand. Context The SKA Mid-frequency Correlator dumps 20100 visibility products from its Matrix style cross correlator function every 190 microseconds. It does this over 20 buses each approximately 312 bits wide, with a total instantaneous bandwidth of over 500 GB/s. This dump of data must be serialised and processed by the long term accumulator to an external DDR4 interface that limits the bandwidth. This is achieved with a debursting buffer that has 20 independent write-ports and a single independent read port. The design requires that the Read more …

Peter Baillie

Project Manager, High Performance Computing Research Laboratory at AUT. Peter’s Project Management role spans across both CSP and SDP Consortia as well as being the Project Manager point of contact to SKA Office. Peter is Project Manager for Low Telescope and reports to Project Manager for CSP Consortium, based in Canada. He also liaises with SDP Resource Management Team for all NZA assigned tasks, outputs and reporting. Peter’s assigned FTE allocation, along with NZA FPGA Developers make-up a significant contribution to the CSIRO / ASTRON / AUT collaboration who is responsible for delivering the Low Correlator and Beamformer design and supporting Read more …

Norbert Abel

Senior Research Engineer, High Performance Computing Research Laboratory, AUT. Norbert is an FPGA engineer, working full time on the SKA project, collaborating closely with ASTRON (Netherlands) and CSIRO (Australia) to develop the Low-frequency Correlator and Beamformer (Low.CBF). He completed his PhD at the University of Heidelberg, Germany, working as FPGA engineer for the new particle accelerator FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. His thesis “Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration” focussed on enabling the widespread use of Partial Reconfiguration by controlling it via a high-level language. After finishing his PhD, Norbert Read more …

Andrew Ensor

Director NZ SKA Alliance, High Performance Computing Research Laboratory, AUT. Andrew is the Director of the New Zealand SKA Alliance, coordinating New Zealand’s significant involvement in the design of the SKA. He has been active in the SKA’s Central Signal Processor and in the Science Data Processor design since 2013. He is also the Director of the High Performance Computing Research Laboratory at AUT. For the SKA project, Andrew has: Developed efficient streaming data compression algorithms which helped form the start up company Nyriad. Lead the Survey correlator design team. Worked on optimising FFT algorithms across a range of hardware Read more …

William Kamp

Senior Research Engineer, High Performance Computing Research Laboratory, AUT. William is an FPGA engineer in the HPCRL, working full time on the SKA project, collaborating closely with NRC (Canada) to develop the Mid-frequency Correlator and Beamformer (Mid.CBF), and with CSIRO (Australia) and ASTRON (Netherlands)to develop the Low.CBF, two of the sub elements of the Central Signal Processor (CSP). For the SKA project, he has developed: An efficient serial data interconnect that will operate across the >20,000 internal 26Gbps optical fibre links of the Mid.CBF. A network communication protocol called AXIoE (Advanced eXtensible Interconnect over Ethernet) designed to extend the internal Read more …