Senior Research Engineer,
High Performance Computing Research Laboratory, AUT.
William is an FPGA engineer in the HPCRL, working full time on the SKA project, collaborating closely with NRC (Canada) to develop the Mid-frequency Correlator and Beamformer (Mid.CBF), and with CSIRO (Australia) and ASTRON (Netherlands)to develop the Low.CBF, two of the sub elements of the Central Signal Processor (CSP).
For the SKA project, he has developed:
- An efficient serial data interconnect that will operate across the >20,000 internal 26Gbps optical fibre links of the Mid.CBF.
- A network communication protocol called AXIoE (Advanced eXtensible Interconnect over Ethernet) designed to extend the internal register buses from a cluster of hundreds of FPGA devices back to a central control computer.
- The cross-correlation function — the raw data ‘blast furnace’ of the mid-frequency SKA Telescope, where all the data from the 197 dish-antenna are cross-multiplied with each other to synthesize a single dish. To do this the requires over 2.4 Peta-operations per second. This machine is on track to be the most energy efficient supercomputer when constructed.
William completed his Ph.D. at the Electrical and Computer Engineering Department at the University of Canterbury. His thesis “Redundant Number Systems for Optimising Digital Signal Processing in Field Programmable Gate Array (FPGA)” considered redundant number systems and their application in optimising digital signal processing in FPGA – making computing machines faster and more efficient by not using binary. He then spent 5 years as an FPGA engineer at Endace Technology Ltd, designing high performance network monitoring equipment using FPGA on PCI-express cards.